As semiconductor technology continues to inch closer to practical limitations in terms of increases in clock speed, architects are increasingly focusing on parallelism in processor architectures to obtain performance improvements. At the integrated circuit device, or chip level, multiple processing cores are often disposed on the same chip, functioning in much the same manner as separate processor chips, or to some extent, as completely separate computers. In addition, even within cores, parallelism is employed through the use of multiple execution units that are specialized to handle certain types of operations. Pipelining is also employed in many instances so that certain operations that may take multiple clock cycles to perform are broken up into stages, enabling other operations to be started prior to completion of earlier operations. Multithreading is also employed to enable multiple instruction streams to be processed in parallel, enabling more overall work to performed in any given clock cycle.
One effect of the increase in the complexity of processor chips, however, is that testing of the manufactured chips has become significantly more complex and time consuming. Early integrated circuit devices often had enough input/output pins to enable all of the relevant internal operations of a device to be monitored to ensure that the device operated in its intended manner. However, with current designs incorporating millions or billions of transistors and numerous additional high level functions, it is impracticable to provide sufficient input/output connectivity to enable direct monitoring of device operation.
To address these limitations, many integrated circuit devices now incorporate a boundary scan architecture within the logic circuitry of a device to provide access to many of the internal circuits of the device. With a boundary scan architecture, one or more serial scan chains, or scan paths, of latches are coupled to an external port of a device, with individual latches embedded within the logic circuitry of the device at key points of the design. The latches, when not specifically configured to operate as a scan chain, do not otherwise alter the functionality of the device. However, when the latches are configured in a specific mode, the latches together operate as a shift register so that data may be shifted into the chain of latches from a single source to simulate different conditions, and so that data generated within a device may be shifted out through a single output. Thus, with a boundary scan architecture, the current state of various circuits in a device at any given time may be recorded and later accessed via external equipment to verify the operation of a manufactured device.
The need to utilize external equipment to perform testing of integrated circuit devices, however, can be a significant burden, particularly for high volume parts. Due to the relatively lower speed of external testing interfaces, a tradeoff often must be made between performing thorough testing that may take several minutes to perform vs. performing a more superficial test in less time, and risking faulty parts being misidentified as good. Furthermore, the need to utilize external equipment often precludes re-testing chips in the field to determine if a new fail has occurred.
Therefore, a significant need continues to exist in the art for a manner of efficiently and cost-effectively testing complex integrated circuit devices such as processor chips and the like.